[phyrrus9]

So, a couple days ago I was talking with @"Ender" and decided I would go out and try to build a real world RISC CPU. Now, I've done similar things before, I've made a few full featured processors, but none of them were anything you could actually use for something. They were either limited by program memory (usually just a few bytes), data memory (mostly nonexistent), instructions available, registers (usually 2 or 4), or bus width (usually 4, 6, or 12).

Sure, there have been processors that fit these specs before, but you don't see them today, the last being the PDP series. So, I decided to modernize it, with a CPU that fits the following:

• Full RISC design
  
• 16 general purpose registers
  
• Large amount of data memory
  
• Large amount of program memory
  
• Security features to prevent executable code from being modified at runtime
  
• 5 stage pipeline (fetch, decode, execute, memory, writeback
  
• Maximum of 1 clock cycle per instruction
  

And my result is this block level diagram.


Now, at this point, that is the only fully complete part of this project. I've made a good deal of progress on it, but it's nowhere close to being done. This is where you come in! If you want to help with this, you get the following:

1. Your name on anything you completed
   
2. Your share of any profits made (if there are. I would like to keep this as open as possible)
   
3. A vast increase in your knowledge of how a CPU works
   

Here's the instruction set I chose, which I borrowed a lot from the ARMv4t architecture, but made changes where I thought I could improve (since we don't support an ISA as large as they do, we got to get some candy features)



So, who's on board?

[Blink]

Note that you people need to be using Windows or Linux (or something that can run Linux bins) to use Quartus (the design tool), and unfortunately I'm usually on neither...

Might just install FreeBSD or Arch on this thing

[phyrrus9]

Ok, well some time has gone by and I've completed quite a bit of work on this project. Right now, you can download the project files here. NOTE: you will need to have Quartus Prime installed with Cyclone V support.

So, what major changes have there been?
I've been doing a lot of work on the pipeline, which as you can see now looks almost completely wired up.

At this point, the only pipeline stage that is missing in this diagram is the write-back, which by far is the easiest stage. The decoder still hasn't been touched, but work has been done on both the execute and memory stages respectively:




Secondly, the instruction fetcher is completed, and you may have noticed from the first image, the stages between the pipeline steps are more defined and stable.


You may have also noticed a new group of DFF's at the bottom of the pipeline. We now have a 4-bit status register!


And finally. I went ahead and organized all of the custom symbols in the project:

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Alright, let me know what you think, and feel free to suggest changes or make your own components.