[Mafia]

I agree that having to order only NAND gates is easy, but easy is not always best. NAND logic sometimes takes more gates than the original to accomplish this task, thus wasting space and adding complexity.

NOT: 1
AND: 2
OR: 3
NOR: 4
XOR: 4
NAND: 1

the same is true for NOR only logic.

NANDs also take up more transistors than standalone gates in most instances.


So, more transistors = more space taken up + more propogation delay (lag), and thus requires a slower clock speed.




I hope this helps you understand a little better.

I see what you mean. Thanks for correcting me, I've only just started getting into electronics, please keep these coming and/or other cool things!