[phyrrus9]

Yeah, sorry for the rather shitty thread title, but I had been pouring over my CPU project and I realized the mistake I may have made. I won't tell it to you, but I will explain everything you need to know. Here is a screenshot of the pipeline of the processor. It's missing a couple major components on the drawing, so I'll just walk you through how it is supposed to operate, and don't worry the part that poses the issue is indeed implemented in the drawing below.

And in case you need more close up images, they're in this spoiler

Spoiler:

Now, let me explain what these components are. Anything you see that has a D on one side and a Q on the other side and not much else is a Flip Flop, which is just a fancy term for memory storage. If you look closely, everything in this diagram has 2 names attached to it. One describes what it is (things like bus_reg_32), and one that describes what it does or is for (like fetch_instruction). Anything that is bus_reg_# is just a bunch of flip flops in parallel, since a flip flop (also called DFF in these diagrams) only stores 1 bit, that number on the end says how many bits it holds.

On to how the pipeline works. This is a very simple 5-stage interlocked continuous pipeline with no fancy tricks going on (branch prediction, stalls, etc). It works like this:

1. Fetch
   
2. Decode
   
3. Execute
   
4. Memory
   
5. Write
   

Here's what they all do:

1. Fetch
Fetch is passed a memory address, and all it does is query RAM for the 32 bits held at that memory address, and then it passes it on to the next stage.

2. Decode
Decode takes that instruction and figures out what it actually means. It does things like figure out if it processes data, talks to RAM, changes the control flow (jump), etc. It also does something special in order to save the step later on: it gets the values of any registers that the instruction needs. Remember that in RISC you can't do any math on memory, you need to load it into a register, which is just a variable that's in hardware on the chip (implemented in this case with flip flops). It then produces some control codes that tell the rest of the pipeline how to handle its operations.

3. Execute
This is the ALU on the chip, it only does math, nothing else. It handles every numeric operation that you can do, and nothing more. This stage is effectively just a calculator. It takes integers in (not registers/variables, but their value), and produces a single integer value as output. This pipeline stage does 2 little extra things in order to keep this simple. It

1. Passes the destination register through unchanged (the decoder passed it to this stage)
   
2. Sets 4 flags (Zero, Negative, Carry, oVerflow) based on its results, and passes them out
   

4. Memory
This is just as basic as the previous stage, and in fact if the previous stage was utilized, this one will not be. It has 2 functions: to read and write to memory, and to ensure that operations complete on time. It has its own stage because some memory operations actually require 2 clock cycles, and so this stage allows those 2-cycle operations to return to the next stage. Note: this is NOT used in the instruction fetch stage.

5. Write
In this step, all of the results that were computed from the previous 2 stages are actually written either to their respective registers or into RAM. It should be noted that this stage is missing from the diagram.

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The Challenge
There is a major problem in this pipeline, and I've even hinted at it using parts of these explanations. As a secondary hint, I will note that a D flip flop is a synchronous device, meaning it will only change value when the clock cycle changes from a 0 to a 1. Likewise this means that all of those bus registers between stages hold their results back until the next clock cycle. Can you spot the problem?

25 NSP if you can spot the problem
50 NSP if you can explain both with assembly (my CPU implements ARMv7) and in words
125NSP if you can explain how to fix the problem
125NSP and +7 rep if you can find a way to do it  without adding more than 50 transistors