[Blink]

I was bored in school today so I designed this CPU:



I call it SZOMPU (I need a catchier name), for Simple/Small Zero Operand Micro Processor Unit.  Made nearly all of it in school today, and finished it after school.  As you can see from the image, it's fairly small.  I designed it similar to Brainfuck, because I started making this after thinking about how Brainfuck uses no operands, and only reads and writes to one cell at a time.  I really like non-orthodox methods of computing and processor design, and this is a good example of that.
I found a neat trick while working on a different CPU (a stack machine), that I used for this one; I use the first bit of every item in ROM as a flag that says if the instruction is data (in which case it should be pushed to the stack, or put into the current cell), or an instruction (to be executed, RIP).  Not a great idea for register-centered CPUs (basically every CPU in use), but it works great for CPUs that mainly work with cache/memory instead of registers (like stack machines).

There aren't really any registers in the CPU.  The one you see in the image (OUTPUT_REG) is there in place of a coprocessor, as the instructions work the same for both.

I also made a hackaday.io page for it, but I've written more in this post.  The Logisim files are there though, idk if you want those, I'll leave the link just in case: https://hackaday.io/project/146481

I may implement this in hardware some day, but I'll leave it in Logisim for now.  (I'll probably make a simulator and assembler soon though)

Note: I am aware that most 16 year olds don't design CPUs when they get bored in class, it's a good thing that I'm not normal

[phyrrus9]

I was bored in school today so I designed this CPU:



I call it SZOMPU (I need a catchier name), for Simple/Small Zero Operand Micro Processor Unit. Made nearly all of it in school today, and finished it after school. As you can see from the image, it's fairly small. I designed it similar to Brainfuck, because I started making this after thinking about how Brainfuck uses no operands, and only reads and writes to one cell at a time. I really like non-orthodox methods of computing and processor design, and this is a good example of that.
I found a neat trick while working on a different CPU (a stack machine), that I used for this one; I use the first bit of every item in ROM as a flag that says if the instruction is data (in which case it should be pushed to the stack, or put into the current cell), or an instruction (to be executed, RIP). Not a great idea for register-centered CPUs (basically every CPU in use), but it works great for CPUs that mainly work with cache/memory instead of registers (like stack machines).

There aren't really any registers in the CPU. The one you see in the image (OUTPUT_REG) is there in place of a coprocessor, as the instructions work the same for both.

I also made a hackaday.io page for it, but I've written more here. The Logisim files are there though, idk if you want those, I'll leave the link just in case: https://hackaday.io/project/146481

I may implement this in hardware some day, but I'll leave it in Logisim for now. (I'll probably make a simulator and assembler soon though)

Note: I am aware that most 16 year olds don't design CPUs when they get bored in class, it's a good thing that I'm not normal

Looks neat, now convert it to an FPGA map so I can test it.

[Blink]

Looks neat, now convert it to an FPGA map so I can test it.

My FPGA should arrive sometime in the near future, so, sure, I will... Assuming it works, ordered it from a somewhat shady seller from China who likely stole them off of Altera/Intel trucks.